The present invention relates to a BiMOS logical circuit, and more particularly to a BiMOS logical circuit including a bipolar transistor at its output stage.
Recently, logic LSIs are strongly required to have large capacity and low power dissipation. Accordingly, there is a tendency that the position of CMOS transistors to meet such requirements is being increasingly elevated. The performance of the CMOS transistors has been considerably improved in recent years by making free use of fining technologies.
A typical logical circuit using such CMOS transistors is shown in FIG. 1. This circuit is composed of four MOS transistors, i.e., two PMOS transistors 1 and 2 and two NMOS transistors 3 and 4, whereby when an input voltage V.sub.IN represents "L" and a control signal .phi. represents "L", an output of "H" is produced as V.sub.OUT and when otherwise, an output of "L" is produced.
However, the circuits using such CMOS transistors have the serious drawback that the operating speed is slower than that of the circuits using bipolar transistors because the current drivability is small. To improve the current drivability, there may be employed a method to increase the capacity of each component. However, this method is not so effective in that the employment thereof results in an increase in the gate capacity. Such a method eventually leads to the bad effect that it runs counter to integration because the area occupation of components becomes large.
To eliminate this, a BiMOS logical circuit using a bipolar transistor at its output stage is employed. FIG. 2 shows an example of such a BiMOS logical circuit. This circuit is composed of seven MOS transistors, i.e., PMOS transistors 5 and 6 and NMOS transistors 7 to 11, and two bipolar transistors 12 and 13. The base currents of the bipolar transistors 12 and 13 are controlled by the MOS transistors and the bipolar transistors are used for the output stage. For this reason, the current drivability is improved and thus a fast operating speed at which the output waveform becomes sharp can be obtained.
FIG. 3 is another example of a BiMOS logical circuit. This circuit is composed of PMOS transistors 14 and 15, NMOS transistors 16 to 18, bipolar transistors 19 and 20, and a diode 21. By the diode 21, the side of the MOS circuit is electrically isolated from the output side.
One problem with the above-mentioned conventional logical circuits is that the number of components increases. For instance, when a circuit constituted solely with CMOS transistors is employed for realizing a certain logic, it is sufficient to use four components as shown in FIG. 1. On the contrary, for realizing the same logic as stated above, when the BiMOS logical circuit shown in FIG. 2 is employed, seven MOS transistors and two bipolar transistors are required, and when the BiMOS logical circuit shown in FIG. 3 is employed, five MOS transistors, two bipolar transistors and one diode are required.
Another problem therewith is that an ideal output level cannot be obtained. For instance, with the shown in FIG. 2, the voltage value at "L" level of the output V.sub.OUT is not equal to the ideal ground level. This is because a voltage difference V.sub.F occurs across the base and emitter of the transistor 13. Accordingly, the voltage value at "L" level of the output V.sub.OUT does not become equal to zero, but becomes equal to V.sub.F. With the circuit shown in FIG. 3, this problem is more serious. Namely, since a current from the output terminal flows into the base of the transistor 20 via the diode 21, the voltage value at "L" level of the output V.sub.OUT becomes equal to a value obtained by adding the forward voltage drop V.sub.D to the base-emitter voltage V.sub.F of the transistor 20. Accordingly, the voltage value at "L" level of the output V.sub.OUT will become equal to a value considerably different from the ideal ground level.